[PATCH] D99418: [AArch64][SVE] Improve codegen for select nodes with fixed types

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7023
+    MVT PredVT = MVT::getVectorVT(SplatValVT, Ty.getVectorElementCount());
+    SDValue SplatVal = DAG.getAnyExtOrTrunc(CCVal, DL, SplatValVT);
+    SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, SplatVal);
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Is this safe?  I know for larger than NEON vectors we'll truncate the mask and thus only care about the bottom bit, however, you're tests show that for NEON sized vectors `bif` is used and so every bit of the mask is meaningful.  I believe this is because it expects the mask to be extended based on `setBooleanVectorContents(ZeroOrNegativeOneBooleanContent)`. Which means a sign extend must be used here to maintain that requirement?


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  https://reviews.llvm.org/D99418/new/

https://reviews.llvm.org/D99418