[PATCH] D99376: [AMDGPU] Mark additional VOP3 as commutable

Tue Mar 30 10:33:18 PDT 2021

Joe_Nash added a comment.

In D99376#2657778 <https://reviews.llvm.org/D99376#2657778>, @rampitec wrote:

> In D99376#2656686 <https://reviews.llvm.org/D99376#2656686>, @Joe_Nash wrote:
>
>> Reverted since I don't fully understand the issue. It passed all tests on my system, but then upon rebasing top of tree it didn't. So I suspect the commutes may not be deterministic/ well constrained.
>
> I have a bad suspicion here: that is not OK to just commute source modifiers for opsel. A DST_OP_SEL shares bits with $src0_modifiers, so it needs to be transferred to the new src0 modifiers and masked in src1. I suspect it does not happen.

Ok I see the issue. In general, how can we tell apart src0 with opsel=1 and dst with opsel=1? 
To avoid issues with commute, I would say don't commute vop3 with 16bit operands. However, V_MAD_I16 and V_MAD_I16_gfx9 do already have isCommute =1. Is this perhaps a bug?

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https://reviews.llvm.org/D99376