[PATCH] D99352: [AMDGPU] ds_read_*/ds_write_* operations require strict alignment.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm requested changes to this revision.
arsenm added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:1407-1408
     if (Size == 64) {
-      // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
-      // aligned, 8 byte access in a single operation using ds_read2/write2_b32
-      // with adjacent offsets.
-      bool AlignedBy4 = Alignment >= Align(4);
+      // ds_read/write_b64 always require 8-byte alignment for performance
+      // reasons.
+      bool AlignedBy8 = Alignment >= Align(8);
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They do not *require* the alignment for performance reasons. This should report whether it works, and isFast for whether we want to prefer it


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  https://reviews.llvm.org/D99352/new/

https://reviews.llvm.org/D99352