[llvm] 292816d - [RISCV] Don't set the SplatOperand flag on intrinsics that take a shift amount.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 30 09:30:25 PDT 2021
Author: Craig Topper
Date: 2021-03-30T09:23:36-07:00
New Revision: 292816d2b613fdf5efbd4287b656bb793ad18e12
URL: https://github.com/llvm/llvm-project/commit/292816d2b613fdf5efbd4287b656bb793ad18e12
DIFF: https://github.com/llvm/llvm-project/commit/292816d2b613fdf5efbd4287b656bb793ad18e12.diff
LOG: [RISCV] Don't set the SplatOperand flag on intrinsics that take a shift amount.
The shift amount should always be a vector or an XLen scalar.
The SplatOperand flag is used to indicate we need to legalize
non-XLen scalars including special handling for i64 on RV32.
This will prevent us from silently adjusting these operands if
the intrinsics are misused.
I'll probably adjust the name of the SplatOperand flag slightly
in a follow up patch.
Reviewed By: khchen, frasercrmck
Differential Revision: https://reviews.llvm.org/D99545
Added:
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 4f1ca49057cb8..bdb9725197975 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -291,6 +291,21 @@ let TargetPrefix = "riscv" in {
[IntrNoMem]>, RISCVVIntrinsic {
let SplatOperand = 3;
}
+ // For destination vector type is the same as first source vector. The
+ // second source operand must match the destination type or be an XLen scalar.
+ // Input: (vector_in, vector_in/scalar_in, vl)
+ class RISCVBinaryAAShiftNoMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_any_ty, llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic;
+ // For destination vector type is the same as first source vector (with mask).
+ // The second source operand must match the destination type or be an XLen scalar.
+ // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
+ class RISCVBinaryAAShiftMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic;
// For destination vector type is NOT the same as first source vector.
// Input: (vector_in, vector_in/scalar_in, vl)
class RISCVBinaryABXNoMask
@@ -308,6 +323,21 @@ let TargetPrefix = "riscv" in {
[IntrNoMem]>, RISCVVIntrinsic {
let SplatOperand = 3;
}
+ // For destination vector type is NOT the same as first source vector. The
+ // second source operand must match the destination type or be an XLen scalar.
+ // Input: (vector_in, vector_in/scalar_in, vl)
+ class RISCVBinaryABShiftNoMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic;
+ // For destination vector type is NOT the same as first source vector (with mask).
+ // The second source operand must match the destination type or be an XLen scalar.
+ // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
+ class RISCVBinaryABShiftMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic;
// For binary operations with V0 as input.
// Input: (vector_in, vector_in/scalar_in, V0, vl)
class RISCVBinaryWithV0
@@ -393,24 +423,39 @@ let TargetPrefix = "riscv" in {
let SplatOperand = 3;
}
// For Saturating binary operations.
+ // The destination vector type is the same as first source vector.
+ // The second source operand matches the destination type or is an XLen scalar.
+ // Input: (vector_in, vector_in/scalar_in, vl)
+ class RISCVSaturatingBinaryAAShiftNoMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_any_ty, llvm_anyint_ty],
+ [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic;
+ // For Saturating binary operations with mask.
+ // The destination vector type is the same as first source vector.
+ // The second source operand matches the destination type or is an XLen scalar.
+ // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
+ class RISCVSaturatingBinaryAAShiftMask
+ : Intrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+ [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic;
+ // For Saturating binary operations.
// The destination vector type is NOT the same as first source vector.
+ // The second source operand matches the destination type or is an XLen scalar.
// Input: (vector_in, vector_in/scalar_in, vl)
- class RISCVSaturatingBinaryABXNoMask
+ class RISCVSaturatingBinaryABShiftNoMask
: Intrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty],
- [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
- let SplatOperand = 2;
- }
+ [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic;
// For Saturating binary operations with mask.
// The destination vector type is NOT the same as first source vector (with mask).
+ // The second source operand matches the destination type or is an XLen scalar.
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
- class RISCVSaturatingBinaryABXMask
+ class RISCVSaturatingBinaryABShiftMask
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
- [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
- let SplatOperand = 3;
- }
+ [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic;
class RISCVTernaryAAAXNoMask
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
@@ -725,6 +770,12 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RISCVBinaryAAXNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVBinaryAAXMask;
}
+ // Like RISCVBinaryAAX, but the second operand is used a shift amount so it
+ // must be a vector or an XLen scalar.
+ multiclass RISCVBinaryAAShift {
+ def "int_riscv_" # NAME : RISCVBinaryAAShiftNoMask;
+ def "int_riscv_" # NAME # "_mask" : RISCVBinaryAAShiftMask;
+ }
multiclass RISCVRGatherVV {
def "int_riscv_" # NAME : RISCVRGatherVVNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVRGatherVVMask;
@@ -743,6 +794,12 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RISCVBinaryABXNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVBinaryABXMask;
}
+ // Like RISCVBinaryABX, but the second operand is used a shift amount so it
+ // must be a vector or an XLen scalar.
+ multiclass RISCVBinaryABShift {
+ def "int_riscv_" # NAME : RISCVBinaryABShiftNoMask;
+ def "int_riscv_" # NAME # "_mask" : RISCVBinaryABShiftMask;
+ }
multiclass RISCVBinaryWithV0 {
def "int_riscv_" # NAME : RISCVBinaryWithV0;
}
@@ -756,9 +813,13 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RISCVSaturatingBinaryAAXNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryAAXMask;
}
- multiclass RISCVSaturatingBinaryABX {
- def "int_riscv_" # NAME : RISCVSaturatingBinaryABXNoMask;
- def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryABXMask;
+ multiclass RISCVSaturatingBinaryAAShift {
+ def "int_riscv_" # NAME : RISCVSaturatingBinaryAAShiftNoMask;
+ def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryAAShiftMask;
+ }
+ multiclass RISCVSaturatingBinaryABShift {
+ def "int_riscv_" # NAME : RISCVSaturatingBinaryABShiftNoMask;
+ def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryABShiftMask;
}
multiclass RISCVTernaryAAAX {
def "int_riscv_" # NAME : RISCVTernaryAAAXNoMask;
@@ -880,12 +941,12 @@ let TargetPrefix = "riscv" in {
defm vor : RISCVBinaryAAX;
defm vxor : RISCVBinaryAAX;
- defm vsll : RISCVBinaryAAX;
- defm vsrl : RISCVBinaryAAX;
- defm vsra : RISCVBinaryAAX;
+ defm vsll : RISCVBinaryAAShift;
+ defm vsrl : RISCVBinaryAAShift;
+ defm vsra : RISCVBinaryAAShift;
- defm vnsrl : RISCVBinaryABX;
- defm vnsra : RISCVBinaryABX;
+ defm vnsrl : RISCVBinaryABShift;
+ defm vnsra : RISCVBinaryABShift;
defm vmseq : RISCVCompare;
defm vmsne : RISCVCompare;
@@ -1023,11 +1084,11 @@ let TargetPrefix = "riscv" in {
defm vsmul : RISCVSaturatingBinaryAAX;
- defm vssrl : RISCVSaturatingBinaryAAX;
- defm vssra : RISCVSaturatingBinaryAAX;
+ defm vssrl : RISCVSaturatingBinaryAAShift;
+ defm vssra : RISCVSaturatingBinaryAAShift;
- defm vnclipu : RISCVSaturatingBinaryABX;
- defm vnclip : RISCVSaturatingBinaryABX;
+ defm vnclipu : RISCVSaturatingBinaryABShift;
+ defm vnclip : RISCVSaturatingBinaryABShift;
defm vmfeq : RISCVCompare;
defm vmfne : RISCVCompare;
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