[PATCH] D99519: [RISCV] Remove floating point condition code legalization from lowerFixedLengthVectorSetccToRVV.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf069000b433c: [RISCV] Remove floating point condition code legalization from… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99519/new/

https://reviews.llvm.org/D99519

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp


Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3459,89 +3459,11 @@
   SDValue VL =
       DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());
 
-  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
-
-  bool Invert = false;
-  Optional<unsigned> LogicOpc;
-  if (ContainerVT.isFloatingPoint()) {
-    bool Swap = false;
-    switch (CC) {
-    default:
-      break;
-    case ISD::SETULE:
-    case ISD::SETULT:
-      Swap = true;
-      LLVM_FALLTHROUGH;
-    case ISD::SETUGE:
-    case ISD::SETUGT:
-      CC = getSetCCInverse(CC, ContainerVT);
-      Invert = true;
-      break;
-    case ISD::SETOGE:
-    case ISD::SETOGT:
-    case ISD::SETGE:
-    case ISD::SETGT:
-      Swap = true;
-      break;
-    case ISD::SETUEQ:
-      // Use !((OLT Op1, Op2) || (OLT Op2, Op1))
-      Invert = true;
-      LogicOpc = RISCVISD::VMOR_VL;
-      CC = ISD::SETOLT;
-      break;
-    case ISD::SETONE:
-      // Use ((OLT Op1, Op2) || (OLT Op2, Op1))
-      LogicOpc = RISCVISD::VMOR_VL;
-      CC = ISD::SETOLT;
-      break;
-    case ISD::SETO:
-      // Use (OEQ Op1, Op1) && (OEQ Op2, Op2)
-      LogicOpc = RISCVISD::VMAND_VL;
-      CC = ISD::SETOEQ;
-      break;
-    case ISD::SETUO:
-      // Use (UNE Op1, Op1) || (UNE Op2, Op2)
-      LogicOpc = RISCVISD::VMOR_VL;
-      CC = ISD::SETUNE;
-      break;
-    }
-
-    if (Swap) {
-      CC = getSetCCSwappedOperands(CC);
-      std::swap(Op1, Op2);
-    }
-  }
-
   MVT MaskVT = MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount());
   SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
 
-  // There are 3 cases we need to emit.
-  // 1. For (OEQ Op1, Op1) && (OEQ Op2, Op2) or (UNE Op1, Op1) || (UNE Op2, Op2)
-  //    we need to compare each operand with itself.
-  // 2. For (OLT Op1, Op2) || (OLT Op2, Op1) we need to compare Op1 and Op2 in
-  //    both orders.
-  // 3. For any other case we just need one compare with Op1 and Op2.
-  SDValue Cmp;
-  if (LogicOpc && (CC == ISD::SETOEQ || CC == ISD::SETUNE)) {
-    Cmp = DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, Op1, Op1,
-                      DAG.getCondCode(CC), Mask, VL);
-    SDValue Cmp2 = DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, Op2, Op2,
-                               DAG.getCondCode(CC), Mask, VL);
-    Cmp = DAG.getNode(*LogicOpc, DL, MaskVT, Cmp, Cmp2, VL);
-  } else {
-    Cmp = DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, Op1, Op2,
-                      DAG.getCondCode(CC), Mask, VL);
-    if (LogicOpc) {
-      SDValue Cmp2 = DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, Op2, Op1,
-                                 DAG.getCondCode(CC), Mask, VL);
-      Cmp = DAG.getNode(*LogicOpc, DL, MaskVT, Cmp, Cmp2, VL);
-    }
-  }
-
-  if (Invert) {
-    SDValue AllOnes = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
-    Cmp = DAG.getNode(RISCVISD::VMXOR_VL, DL, MaskVT, Cmp, AllOnes, VL);
-  }
+  SDValue Cmp = DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, Op1, Op2,
+                            Op.getOperand(2), Mask, VL);
 
   return convertFromScalableVector(VT, Cmp, DAG, Subtarget);
 }


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