[PATCH] D98716: [NFC][CodeGen] Separate TargetRegisterInfo needsStackRealignment and canRealignStack

[Tomas Matheson via Phabricator via llvm-commits]

tmatheson updated this revision to Diff 334109.
tmatheson added a comment.
Herald added subscribers: frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, edward-jones, zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, kbarton, aheejin, jgravelle-google, sbc100, nemanjai, sdardis, dschuff, jholewinski.

Update with new names: shouldRealignStack/canRealignStack/hasStackRealignment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98716/new/

https://reviews.llvm.org/D98716

Files:
  llvm/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
  llvm/lib/CodeGen/GCRootLowering.cpp
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/MachineFrameInfo.cpp
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/StackMaps.cpp
  llvm/lib/CodeGen/TargetRegisterInfo.cpp
  llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/ARC/ARCFrameLowering.cpp
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
  llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp
  llvm/lib/Target/M68k/M68kFrameLowering.cpp
  llvm/lib/Target/M68k/M68kISelLowering.cpp
  llvm/lib/Target/M68k/M68kRegisterInfo.cpp
  llvm/lib/Target/Mips/MipsFrameLowering.cpp
  llvm/lib/Target/Mips/MipsRegisterInfo.cpp
  llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
  llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/Sparc/SparcFrameLowering.cpp
  llvm/lib/Target/VE/VEFrameLowering.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
  llvm/lib/Target/X86/X86FrameLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.cpp

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