[PATCH] D98002: [RISCV] Add scheduling resources for V

PeiHsiangHung via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 29 17:58:03 PDT 2021

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NickHung added a comment.

Adding those "sched" information into base RVV instructions seems redundant? The scheduler works on PseudoRVV instructions.
SchedReadWrite needs to consider pseudo instructions with LMUL? Their latency should be different.


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  https://reviews.llvm.org/D98002/new/

https://reviews.llvm.org/D98002

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