[llvm] 247ff26 - [AArch64][GlobalISel] NFC: Replace IR regbankselect test with MIR test

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2021-03-29T16:32:34-07:00
New Revision: 247ff26a89673886c20a3199c4aa0614b1b5c45d

URL: https://github.com/llvm/llvm-project/commit/247ff26a89673886c20a3199c4aa0614b1b5c45d
DIFF: https://github.com/llvm/llvm-project/commit/247ff26a89673886c20a3199c4aa0614b1b5c45d.diff

LOG: [AArch64][GlobalISel] NFC: Replace IR regbankselect test with MIR test

regbank-ceil.ll -> regbank-ceil.mir

The IR test was intended to only check register banks. This makes it brittle,
especially as we improve load/store combines in GlobalISel.

Rewriting this as a MIR test also makes it more consistent with the rest of
the testcases in GlobalISel.

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir

Modified: 
    

Removed: 
    llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll
deleted file mode 100644
index b7bc230fb471..000000000000
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-; RUN: llc -O=0 -verify-machineinstrs -mtriple aarch64--- \
-; RUN: -stop-before=instruction-select -global-isel %s -o - | FileCheck %s
-
-; Make sure that we choose a FPR for the G_FCEIL and G_LOAD instead of a GPR.
-
-declare float @llvm.ceil.f32(float)
-
-; CHECK-LABEL: name:            foo
-define float @foo(float) {
-  store float %0, float* undef, align 4
-  ; CHECK: %2:fpr(s32) = G_LOAD %1(p0)
-  ; CHECK-NEXT: %3:fpr(s32) = G_FCEIL %2
-  %2 = load float, float* undef, align 4
-  %3 = call float @llvm.ceil.f32(float %2)
-  ret float %3
-}

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
new file mode 100644
index 000000000000..bab588487635
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name:            load_gets_fpr
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: load_gets_fpr
+    ; CHECK: liveins: $x0
+    ; CHECK: %ptr:gpr(p0) = COPY $x0
+    ; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load 4)
+    ; CHECK: %fceil:fpr(s32) = G_FCEIL %load
+    ; CHECK: $s0 = COPY %fceil(s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %ptr:_(p0) = COPY $x0
+    %load:_(s32) = G_LOAD %ptr(p0) :: (load 4)
+    %fceil:_(s32) = G_FCEIL %load
+    $s0 = COPY %fceil:_(s32)
+    RET_ReallyLR implicit $s0
+
+...