[llvm] 96d14ff - [NFC][RISCV] Pass file through update_llc_tests to fix whitespace issues
Roger Ferrer Ibanez via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 29 10:03:03 PDT 2021
Author: Roger Ferrer Ibanez
Date: 2021-03-29T17:02:47Z
New Revision: 96d14ff505bf47da6aa82e170c25733c67224a05
URL: https://github.com/llvm/llvm-project/commit/96d14ff505bf47da6aa82e170c25733c67224a05
DIFF: https://github.com/llvm/llvm-project/commit/96d14ff505bf47da6aa82e170c25733c67224a05.diff
LOG: [NFC][RISCV] Pass file through update_llc_tests to fix whitespace issues
While addressing RVV frame layout issues I found this file had
whitespace differences that made diffs noisier than they should be.
Differential Revision: https://reviews.llvm.org/D98800
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
index eca83c26a1c3..62ac11464c55 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
@@ -1,39 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+m -verify-machineinstrs < %s | FileCheck %s
define void @rvv_vla(i64 %n, i64 %i) nounwind {
; CHECK-LABEL: rvv_vla:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -32
-; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; CHECK-NEXT: addi s0, sp, 32
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: addi a3, zero, 3
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, 15
-; CHECK-NEXT: andi a0, a0, -16
-; CHECK-NEXT: sub a0, sp, a0
-; CHECK-NEXT: mv sp, a0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: sub a2, s0, a2
-; CHECK-NEXT: addi a2, a2, -32
-; CHECK-NEXT: vl1re64.v v25, (a2)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: addi a3, zero, 3
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: sub a2, s0, a2
-; CHECK-NEXT: addi a2, a2, -32
-; CHECK-NEXT: vl2re64.v v26, (a2)
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: lw a0, 0(a0)
-; CHECK-NEXT: addi sp, s0, -32
-; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 32
-; CHECK-NEXT: ret
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi s0, sp, 32
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: addi a3, zero, 3
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: sub sp, sp, a2
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: addi a0, a0, 15
+; CHECK-NEXT: andi a0, a0, -16
+; CHECK-NEXT: sub a0, sp, a0
+; CHECK-NEXT: mv sp, a0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: sub a2, s0, a2
+; CHECK-NEXT: addi a2, a2, -32
+; CHECK-NEXT: vl1re64.v v25, (a2)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: addi a3, zero, 3
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: sub a2, s0, a2
+; CHECK-NEXT: addi a2, a2, -32
+; CHECK-NEXT: vl2re64.v v26, (a2)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: lw a0, 0(a0)
+; CHECK-NEXT: addi sp, s0, -32
+; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 32
+; CHECK-NEXT: ret
%vla.addr = alloca i32, i64 %n
%v1.addr = alloca <vscale x 1 x i64>
@@ -50,28 +51,28 @@ define void @rvv_vla(i64 %n, i64 %i) nounwind {
define void @rvv_overaligned() nounwind {
; CHECK-LABEL: rvv_overaligned:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -128
-; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
-; CHECK-NEXT: addi s0, sp, 128
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: andi sp, sp, -64
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 112
-; CHECK-NEXT: vl1re64.v v25, (a0)
-; CHECK-NEXT: addi a0, sp, 112
-; CHECK-NEXT: vl2re64.v v26, (a0)
-; CHECK-NEXT: lw a0, 64(sp)
-; CHECK-NEXT: addi sp, s0, -128
-; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 128
-; CHECK-NEXT: ret
+; CHECK-NEXT: addi sp, sp, -128
+; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi s0, sp, 128
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: addi a1, zero, 3
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: andi sp, sp, -64
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 112
+; CHECK-NEXT: vl1re64.v v25, (a0)
+; CHECK-NEXT: addi a0, sp, 112
+; CHECK-NEXT: vl2re64.v v26, (a0)
+; CHECK-NEXT: lw a0, 64(sp)
+; CHECK-NEXT: addi sp, s0, -128
+; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 128
+; CHECK-NEXT: ret
%overaligned = alloca i32, align 64
%v1.addr = alloca <vscale x 1 x i64>
@@ -85,41 +86,41 @@ define void @rvv_overaligned() nounwind {
}
define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
-; CHECK-LABEL: rvv_vla_and_overaligned
+; CHECK-LABEL: rvv_vla_and_overaligned:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -128
-; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s1, 104(sp) # 8-byte Folded Spill
-; CHECK-NEXT: addi s0, sp, 128
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: addi a3, zero, 3
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: andi sp, sp, -64
-; CHECK-NEXT: mv s1, sp
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: addi a0, a0, 15
-; CHECK-NEXT: andi a0, a0, -16
-; CHECK-NEXT: sub a0, sp, a0
-; CHECK-NEXT: mv sp, a0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, s1, a2
-; CHECK-NEXT: addi a2, a2, 96
-; CHECK-NEXT: vl1re64.v v25, (a2)
-; CHECK-NEXT: addi a2, s1, 96
-; CHECK-NEXT: vl2re64.v v26, (a2)
-; CHECK-NEXT: lw a2, 64(s1)
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: lw a0, 0(a0)
-; CHECK-NEXT: addi sp, s0, -128
-; CHECK-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 128
-; CHECK-NEXT: ret
+; CHECK-NEXT: addi sp, sp, -128
+; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s1, 104(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi s0, sp, 128
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: addi a3, zero, 3
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: sub sp, sp, a2
+; CHECK-NEXT: andi sp, sp, -64
+; CHECK-NEXT: mv s1, sp
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: addi a0, a0, 15
+; CHECK-NEXT: andi a0, a0, -16
+; CHECK-NEXT: sub a0, sp, a0
+; CHECK-NEXT: mv sp, a0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, s1, a2
+; CHECK-NEXT: addi a2, a2, 96
+; CHECK-NEXT: vl1re64.v v25, (a2)
+; CHECK-NEXT: addi a2, s1, 96
+; CHECK-NEXT: vl2re64.v v26, (a2)
+; CHECK-NEXT: lw a2, 64(s1)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: lw a0, 0(a0)
+; CHECK-NEXT: addi sp, s0, -128
+; CHECK-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 128
+; CHECK-NEXT: ret
%overaligned = alloca i32, align 64
%vla.addr = alloca i32, i64 %n
@@ -134,4 +135,4 @@ define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
%s2 = load volatile i32, i32* %p
ret void
-}
\ No newline at end of file
+}
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