[PATCH] D99123: [SampleFDO] Flow Sensitive Sample FDO (FSAFDO)

Snehasish Kumar via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 29 09:45:10 PDT 2021


snehasish added inline comments.


================
Comment at: llvm/include/llvm/Support/FSAFDODiscriminator.h:19
+
+#define PASS_1_DIS_BIT_BEG 8
+#define PASS_1_DIS_BIT_END 13
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A few questions about the discriminator bits:

* Depending on the transformation in the target pass the requirement of bits may be different, i.e. 5 bits for each may be too many or too few. Do you have any data to share about how many bits are used by each?

* How do we alert authors of new target optimizations (or code refactoring) additional discriminator bits are needed to disambiguate? Would a late stage analysis only pass which enumerates different instructions with the same debug+discriminator info be useful to commit?

* If I understand correctly, we bump the bit for each level of cloning. This seems to be a less efficient coding scheme, max 5 bits where by enumeration you could identify 31 clones? Have you considered other coding schemes?


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  https://reviews.llvm.org/D99123/new/

https://reviews.llvm.org/D99123



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