[PATCH] D99492: [RISCV] "V" Extention coming with "F" "D" "Zfh"

[Jim Lin via Phabricator via llvm-commits]

Jim added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:139
+    for (MVT VT : F64VecVTs)
+      addRegClassForRVV(VT);
 
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It is incorrect. Only Zfh imply F enabled and D imply F enabled.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99492/new/

https://reviews.llvm.org/D99492