[llvm] 4d5ee71 - [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 26 16:46:33 PDT 2021
Author: Craig Topper
Date: 2021-03-26T16:37:20-07:00
New Revision: 4d5ee71b52657ef8871a34d91fe41f8a339e96f3
URL: https://github.com/llvm/llvm-project/commit/4d5ee71b52657ef8871a34d91fe41f8a339e96f3
DIFF: https://github.com/llvm/llvm-project/commit/4d5ee71b52657ef8871a34d91fe41f8a339e96f3.diff
LOG: [RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC
It's unlikely that FMADD and FMSUB would have different scheduling
information so merge them.
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D99140
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVSchedule.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 080156c624da..1e551cca7ef2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -82,16 +82,16 @@ def FSD : RVInstS<0b011, OPC_STORE_FP, (outs),
Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>;
def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">,
- Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
+ Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">;
def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">,
- Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
+ Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">;
def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">,
- Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
+ Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">;
def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">,
- Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
+ Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">;
def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index c041a11cc67c..2ca439c096f4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -117,16 +117,16 @@ def FSW : RVInstS<0b010, OPC_STORE_FP, (outs),
Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>;
def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">,
- Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
+ Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">;
def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">,
- Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
+ Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">;
def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">,
- Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
+ Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">;
def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">,
- Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
+ Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">;
def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index bb0cb59db0e2..9337501a5a30 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -83,16 +83,16 @@ def FSH : RVInstS<0b001, OPC_STORE_FP, (outs),
Sched<[WriteFST16, ReadStoreData, ReadFMemBase]>;
def FMADD_H : FPFMAH_rrr_frm<OPC_MADD, "fmadd.h">,
- Sched<[WriteFMulAdd16, ReadFMulAdd16, ReadFMulAdd16, ReadFMulAdd16]>;
+ Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
def : FPFMAHDynFrmAlias<FMADD_H, "fmadd.h">;
def FMSUB_H : FPFMAH_rrr_frm<OPC_MSUB, "fmsub.h">,
- Sched<[WriteFMulSub16, ReadFMulSub16, ReadFMulSub16, ReadFMulSub16]>;
+ Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
def : FPFMAHDynFrmAlias<FMSUB_H, "fmsub.h">;
def FNMSUB_H : FPFMAH_rrr_frm<OPC_NMSUB, "fnmsub.h">,
- Sched<[WriteFMulSub16, ReadFMulSub16, ReadFMulSub16, ReadFMulSub16]>;
+ Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
def : FPFMAHDynFrmAlias<FNMSUB_H, "fnmsub.h">;
def FNMADD_H : FPFMAH_rrr_frm<OPC_NMADD, "fnmadd.h">,
- Sched<[WriteFMulAdd16, ReadFMulAdd16, ReadFMulAdd16, ReadFMulAdd16]>;
+ Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
def : FPFMAHDynFrmAlias<FNMADD_H, "fnmadd.h">;
def FADD_H : FPALUH_rr_frm<0b0000010, "fadd.h">,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 125b1c9ddc74..c5bce7e82ad3 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -145,14 +145,12 @@ def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>;
// FP multiplication
let Latency = 5 in {
def : WriteRes<WriteFMul32, [RocketUnitFPALU]>;
-def : WriteRes<WriteFMulAdd32, [RocketUnitFPALU]>;
-def : WriteRes<WriteFMulSub32, [RocketUnitFPALU]>;
+def : WriteRes<WriteFMA32, [RocketUnitFPALU]>;
}
let Latency = 7 in {
def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;
-def : WriteRes<WriteFMulAdd64, [RocketUnitFPALU]>;
-def : WriteRes<WriteFMulSub64, [RocketUnitFPALU]>;
+def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
}
// FP division
@@ -203,11 +201,9 @@ def : ReadAdvance<ReadFMemBase, 0>;
def : ReadAdvance<ReadFALU32, 0>;
def : ReadAdvance<ReadFALU64, 0>;
def : ReadAdvance<ReadFMul32, 0>;
-def : ReadAdvance<ReadFMulAdd32, 0>;
-def : ReadAdvance<ReadFMulSub32, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
def : ReadAdvance<ReadFMul64, 0>;
-def : ReadAdvance<ReadFMulAdd64, 0>;
-def : ReadAdvance<ReadFMulSub64, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
def : ReadAdvance<ReadFDiv32, 0>;
def : ReadAdvance<ReadFDiv64, 0>;
def : ReadAdvance<ReadFSqrt32, 0>;
@@ -250,9 +246,8 @@ def : WriteRes<WriteFCvtF16ToI32, []>;
def : WriteRes<WriteFDiv16, []>;
def : WriteRes<WriteFCmp16, []>;
def : WriteRes<WriteFLD16, []>;
-def : WriteRes<WriteFMulAdd16, []>;
+def : WriteRes<WriteFMA16, []>;
def : WriteRes<WriteFMinMax16, []>;
-def : WriteRes<WriteFMulSub16, []>;
def : WriteRes<WriteFMul16, []>;
def : WriteRes<WriteFMovI16ToF16, []>;
def : WriteRes<WriteFMovF16ToI16, []>;
@@ -272,9 +267,8 @@ def : ReadAdvance<ReadFCvtF16ToF32, 0>;
def : ReadAdvance<ReadFCvtF16ToI32, 0>;
def : ReadAdvance<ReadFDiv16, 0>;
def : ReadAdvance<ReadFCmp16, 0>;
-def : ReadAdvance<ReadFMulAdd16, 0>;
+def : ReadAdvance<ReadFMA16, 0>;
def : ReadAdvance<ReadFMinMax16, 0>;
-def : ReadAdvance<ReadFMulSub16, 0>;
def : ReadAdvance<ReadFMul16, 0>;
def : ReadAdvance<ReadFMovI16ToF16, 0>;
def : ReadAdvance<ReadFMovF16ToI16, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index d06b52ffa458..07ec052e0491 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -103,8 +103,7 @@ def : WriteRes<WriteAtomicLDD, [SiFive7PipeA]>;
let Latency = 5 in {
def : WriteRes<WriteFALU32, [SiFive7PipeB]>;
def : WriteRes<WriteFMul32, [SiFive7PipeB]>;
-def : WriteRes<WriteFMulAdd32, [SiFive7PipeB]>;
-def : WriteRes<WriteFMulSub32, [SiFive7PipeB]>;
+def : WriteRes<WriteFMA32, [SiFive7PipeB]>;
}
let Latency = 3 in {
def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>;
@@ -120,8 +119,7 @@ def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
let Latency = 7 in {
def : WriteRes<WriteFALU64, [SiFive7PipeB]>;
def : WriteRes<WriteFMul64, [SiFive7PipeB]>;
-def : WriteRes<WriteFMulAdd64, [SiFive7PipeB]>;
-def : WriteRes<WriteFMulSub64, [SiFive7PipeB]>;
+def : WriteRes<WriteFMA64, [SiFive7PipeB]>;
}
let Latency = 3 in {
def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>;
@@ -191,11 +189,9 @@ def : ReadAdvance<ReadFMemBase, 0>;
def : ReadAdvance<ReadFALU32, 0>;
def : ReadAdvance<ReadFALU64, 0>;
def : ReadAdvance<ReadFMul32, 0>;
-def : ReadAdvance<ReadFMulAdd32, 0>;
-def : ReadAdvance<ReadFMulSub32, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
def : ReadAdvance<ReadFMul64, 0>;
-def : ReadAdvance<ReadFMulAdd64, 0>;
-def : ReadAdvance<ReadFMulSub64, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
def : ReadAdvance<ReadFDiv32, 0>;
def : ReadAdvance<ReadFDiv64, 0>;
def : ReadAdvance<ReadFSqrt32, 0>;
@@ -238,9 +234,8 @@ def : WriteRes<WriteFCvtF16ToI32, []>;
def : WriteRes<WriteFDiv16, []>;
def : WriteRes<WriteFCmp16, []>;
def : WriteRes<WriteFLD16, []>;
-def : WriteRes<WriteFMulAdd16, []>;
+def : WriteRes<WriteFMA16, []>;
def : WriteRes<WriteFMinMax16, []>;
-def : WriteRes<WriteFMulSub16, []>;
def : WriteRes<WriteFMul16, []>;
def : WriteRes<WriteFMovI16ToF16, []>;
def : WriteRes<WriteFMovF16ToI16, []>;
@@ -260,9 +255,8 @@ def : ReadAdvance<ReadFCvtF16ToF32, 0>;
def : ReadAdvance<ReadFCvtF16ToI32, 0>;
def : ReadAdvance<ReadFDiv16, 0>;
def : ReadAdvance<ReadFCmp16, 0>;
-def : ReadAdvance<ReadFMulAdd16, 0>;
+def : ReadAdvance<ReadFMA16, 0>;
def : ReadAdvance<ReadFMinMax16, 0>;
-def : ReadAdvance<ReadFMulSub16, 0>;
def : ReadAdvance<ReadFMul16, 0>;
def : ReadAdvance<ReadFMovI16ToF16, 0>;
def : ReadAdvance<ReadFMovF16ToI16, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
index 030b63c96ad2..4882aa809266 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedule.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -42,14 +42,11 @@ def WriteFALU16 : SchedWrite; // FP 16-bit computation
def WriteFALU32 : SchedWrite; // FP 32-bit computation
def WriteFALU64 : SchedWrite; // FP 64-bit computation
def WriteFMul16 : SchedWrite; // 16-bit floating point multiply
-def WriteFMulAdd16 : SchedWrite; // 16-bit floating point multiply add
-def WriteFMulSub16 : SchedWrite; // 16-bit floating point multiply sub
+def WriteFMA16 : SchedWrite; // 16-bit floating point fused multiply-add
def WriteFMul32 : SchedWrite; // 32-bit floating point multiply
-def WriteFMulAdd32 : SchedWrite; // 32-bit floating point multiply add
-def WriteFMulSub32 : SchedWrite; // 32-bit floating point multiply sub
+def WriteFMA32 : SchedWrite; // 32-bit floating point fused multiply-add
def WriteFMul64 : SchedWrite; // 64-bit floating point multiply
-def WriteFMulAdd64 : SchedWrite; // 64-bit floating point multiply add
-def WriteFMulSub64 : SchedWrite; // 64-bit floating point multiply sub
+def WriteFMA64 : SchedWrite; // 64-bit floating point fused multiply-add
def WriteFDiv16 : SchedWrite; // 16-bit floating point divide
def WriteFDiv32 : SchedWrite; // 32-bit floating point divide
def WriteFDiv64 : SchedWrite; // 64-bit floating point divide
@@ -155,14 +152,11 @@ def ReadFALU16 : SchedRead; // FP 16-bit computation
def ReadFALU32 : SchedRead; // FP 32-bit computation
def ReadFALU64 : SchedRead; // FP 64-bit computation
def ReadFMul16 : SchedRead; // 16-bit floating point multiply
-def ReadFMulAdd16 : SchedRead; // 16-bit floating point multiply add
-def ReadFMulSub16 : SchedRead; // 16-bit floating point multiply sub
+def ReadFMA16 : SchedRead; // 16-bit floating point fused multiply-add
def ReadFMul32 : SchedRead; // 32-bit floating point multiply
-def ReadFMulAdd32 : SchedRead; // 32-bit floating point multiply add
-def ReadFMulSub32 : SchedRead; // 32-bit floating point multiply sub
+def ReadFMA32 : SchedRead; // 32-bit floating point fused multiply-add
def ReadFMul64 : SchedRead; // 64-bit floating point multiply
-def ReadFMulAdd64 : SchedRead; // 64-bit floating point multiply add
-def ReadFMulSub64 : SchedRead; // 64-bit floating point multiply sub
+def ReadFMA64 : SchedRead; // 64-bit floating point fused multiply-add
def ReadFDiv16 : SchedRead; // 16-bit floating point divide
def ReadFDiv32 : SchedRead; // 32-bit floating point divide
def ReadFDiv64 : SchedRead; // 64-bit floating point divide
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