[PATCH] D99437: [AArch64] Fix lowering zext/sext of v64i1.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: david-arm, dmgreen, t.p.northover, aemerson.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
fhahn requested review of this revision.
Herald added a project: LLVM.

Currently performExtendCombine assumes that the src-element bitwidth * 2
is a valid MVT. But this is not the case for i1 and it causes a crash on
the v64i1 test cases added in this patch.

To fix the crash, do not try to perform the transformation if the
widened source element type is not valid.

The code generated is not great, but that could be improved as follow-up.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99437

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll

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