[PATCH] D99352: [AMDGPU] ds_read_*/ds_write_* operations require strict alignment.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

@foad can we run it trough gfx perf suite? With exception of one ds_write_b64 store it seems reasonable to me. Of course these splits to b8 would be unfortunate but I assume it shall not happen in real life too often and the data is usually better aligned.



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Comment at: llvm/test/CodeGen/AMDGPU/ds_write2.ll:849
+; GFX9-UNALIGNED-NEXT:  v_mov_b32_e32 v3, s3
+; GFX9-UNALIGNED-NEXT:  ds_write2_b64 v4, v[0:1], v[2:3] offset1:1
+; GFX9-UNALIGNED-NEXT:  s_endpgm
----------------
It seems it misses the same split to b32.


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  https://reviews.llvm.org/D99352/new/

https://reviews.llvm.org/D99352