[PATCH] D98169: [PoC][IR] Permit load/store/alloca for struct with the same scalable vectors.
Hsiangkai Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 24 00:10:17 PDT 2021
HsiangKai updated this revision to Diff 332876.
HsiangKai added a comment.
Herald added subscribers: kerbowa, pengfei, nhaehnle, jvesely, arsenm, jholewinski.
Use TypeSize for offsets instead of StackOffset.
The memebers are all scalable or all fixed objects. We could use TypeSize for offsets. In other places in the current implementation, it uses TypeSize as the offset type. Use TypeSize for member offsets is more consistent with the current implementation.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D98169/new/
https://reviews.llvm.org/D98169
Files:
llvm/include/llvm/CodeGen/Analysis.h
llvm/include/llvm/IR/DataLayout.h
llvm/include/llvm/IR/Type.h
llvm/lib/Analysis/ConstantFolding.cpp
llvm/lib/Analysis/MemoryBuiltins.cpp
llvm/lib/Analysis/ScalarEvolution.cpp
llvm/lib/CodeGen/Analysis.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/IR/DataLayout.cpp
llvm/lib/IR/Type.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/lib/Target/X86/X86CallLowering.cpp
llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
llvm/lib/Transforms/IPO/AttributorAttributes.cpp
llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/lib/Transforms/Scalar/SROA.cpp
llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
llvm/test/CodeGen/RISCV/rvv/load-store-scalable-struct.ll
llvm/test/Other/load-scalable-vector-struct.ll
llvm/test/Other/store-scalable-vector-struct.ll
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