[PATCH] D99324: [AArch64][SVE] Simplify codegen of svdup_lane intrinsic

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

In D99324#2652288 <https://reviews.llvm.org/D99324#2652288>, @bin.cheng-ali wrote:

> Excuse me, I am new to LLVM/backend, one question is: What does "stock LLVM IR" mean(refer to) in above comment?

By stock LLVM IR I'm referring to the LLVM instructions as defined by the LandRef plus non-target specific intrinsics.

> As for the patch, I am trying to understand the issue, do you suggest we should first introduce DUP_LANE pattern similar to SVDOT_LANE_S so that clang CodeGen doesn't generate dup.x when possible?

I'm not sure I fully understand your question but in general when it comes to code generation I'm trying to ensure where possible that we have a canonicalised representation so that we minimise the number of patterns (IR or DAG) that end up resolving to the same instruction.


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