[llvm] d92b495 - [AMDGPU] Inline FSHRPattern into its only use. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-03-26T09:32:02Z
New Revision: d92b4956d6db8904f6a21c0e037dd5161b843b87

URL: https://github.com/llvm/llvm-project/commit/d92b4956d6db8904f6a21c0e037dd5161b843b87
DIFF: https://github.com/llvm/llvm-project/commit/d92b4956d6db8904f6a21c0e037dd5161b843b87.diff

LOG: [AMDGPU] Inline FSHRPattern into its only use. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
    llvm/lib/Target/AMDGPU/EvergreenInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 8ef9c99e8b35..9b177088a2aa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -596,12 +596,6 @@ class DwordAddrPat<ValueType vt, RegisterClass rc> : AMDGPUPat <
   (vt rc:$addr)
 >;
 
-// fshr pattern
-class FSHRPattern <Instruction BIT_ALIGN> : AMDGPUPat <
-  (fshr i32:$src0, i32:$src1, i32:$src2),
-  (BIT_ALIGN $src0, $src1, $src2)
->;
-
 // rotr pattern
 class ROTRPattern <Instruction BIT_ALIGN> : AMDGPUPat <
   (rotr i32:$src0, i32:$src1),

diff  --git a/llvm/lib/Target/AMDGPU/EvergreenInstructions.td b/llvm/lib/Target/AMDGPU/EvergreenInstructions.td
index 8d3e138ba56a..596c3d7baea0 100644
--- a/llvm/lib/Target/AMDGPU/EvergreenInstructions.td
+++ b/llvm/lib/Target/AMDGPU/EvergreenInstructions.td
@@ -532,7 +532,10 @@ def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
 def : UMad24Pat<MULADD_UINT24_eg>;
 
 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
-def : FSHRPattern <BIT_ALIGN_INT_eg>;
+def : AMDGPUPat <
+  (fshr i32:$src0, i32:$src1, i32:$src2),
+  (BIT_ALIGN_INT_eg $src0, $src1, $src2)
+>;
 def : ROTRPattern <BIT_ALIGN_INT_eg>;
 def MULADD_eg : MULADD_Common<0x14>;
 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;