[PATCH] D99352: [AMDGPU] ds_read_*/ds_write_* operations require strict alignment.

[Mahesha S via Phabricator via llvm-commits]

hsmhsm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:1434-1435
     if (Size == 128) {
-      // ds_read/write_b128 require 16-byte alignment on gfx8 and older, but we
-      // can do a 8 byte aligned, 16 byte access in a single operation using
-      // ds_read2/write2_b64.
-      bool Aligned = Alignment >= Align(8);
+      // ds_read/write_b128 require 16-byte alignment on gfx8 and older.
+      bool Aligned = Alignment >= Align(16);
       if (IsFast)
----------------
foad wrote:
> I don't see the reason for this change. Everything the old comment said is still true.
We have updated the .td file to be strictly aligned irrespective of if "unaligned access mode" is enabled or not. But, here we are relaxing it if we are not having above changes, and hence both glboal ISel and SDAG ISel breaks down in certain cases. Please try the test "lds-misaligned-bug.ll",  both glboal ISel and SDAG ISel asserts for this test, without above change and with only changes to .td file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99352/new/

https://reviews.llvm.org/D99352