[PATCH] D97909: [AIX] Allow safe for 32bit P8 VSX pattern matching

[Zarko Todorovski via Phabricator via llvm-commits]

ZarkoCA added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2204
+  //  BE variable double 32-bit version
+  dag BE_32B_VDWORD_PERM_VEC = (v16i8 (LVSL (i32 ZERO),
+                                        (RLWINM (ANDI_rec $Idx, 1), 3, 0, 28)));
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This was giving me trouble and @nemanjai helped.  Since the 32bit PPC implementation needs to account for SPE, the definition of `GPRC_NOR0` requires we type `ZERO`.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:3195
+def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
+          (f32 VectorExtractions.BE_VARIABLE_FLOAT)>;
 
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nemanjai wrote:
> Moving this here is just half the story. You will also have to add a 32-bit version of this along with the respective test. It should be straightforward to implement
> `VectorExtractions.BE_32B_VARIABLE_FLOAT` - just use `RLWINM` instead of `RLDICR`.
> 
> The test to add would be something like:
> ```
> define float @test(<4 x float> %a, i32 %idx) local_unnamed_addr #0 {
> entry:
>   %vecext = extractelement <4 x float> %a, i32 %idx
>   ret float %vecext
> }
> ```
I added this and a 32bit version of variable double extraction as well. 

Thank you for the offline help in addressing the issues in implementing this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97909/new/

https://reviews.llvm.org/D97909