[PATCH] D98625: [AArch64][SVE] Lower fixed length EXTRACT_VECTOR_ELT

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9960
 
+  SDValue Op0 = Op.getOperand(0);
+  EVT VT = Op0.getValueType();
----------------
Are there any uses of this? If not then you may as well preserve the original `EVT VT = Op.getOperand(0).getValueType();`


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll:93
+
+define float @extractelement_v4f32(<4 x float>* %a) #0 {
+; CHECK-LABEL: extractelement_v4f32:
----------------
This falls under my previous "The tests that take 64/128 bit vectors should pass the vector parameter directly rather than by reference." comment.

There should also be a `<2 x float>` test.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll:150
+
+define double @extractelement_v4f64(<4 x double>* %a) #0 {
+; CHECK-LABEL: extractelement_v4f64:
----------------
You're missing tests for `<1 x double>` and `<2 x double>`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98625/new/

https://reviews.llvm.org/D98625