[PATCH] D99324: [AArch64][SVE] Simplify codegen of svdup_lane intrinsic

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

>> OK, I understand you point. splat_vector(extract_vector_elt(vec, idx)) looks ok for me, and why you prefer do it in in SVEIntrinsicOpts.cpp ? what about do this  in performdagcombine  with AArch64TBL node?
>
> The reason i prefer to handle in performdagcombine  is that what we want to match is AArch64tbl ( ... splat_vector(..., constant)) rather than sve.tbl + sve.dupx. Since shufflevector can also convert to splat_vector.

I feel the higher up the chain/earlier we do this the better.  Outside of the ACLE intrinsics I wouldn't expect scalable AArch64ISD::TBL to be created unless that's exactly what the code generator wants.  It's worth highlighting that this sort of `SVE ACLE intrinsics -> LLVM IR` transform will not be an isolated case.  We deliberately created intrinsics even for common transforms so that we could minimise use of stock LLVM IR and thus limit failures due to missing scalable vector support.  As LLVM matures I would expect us to utilise stock LLVM IR more and more.  For example converting `dup`'s to shufflevector, `ptrue all` predicated operations to normal LLVM bin ops...etc.

That said, if you think PerformDAGCombine (presumable performIntrinsicCombine) is the best place today then fine.  It can easily be moved up the chain when we're more comfortable.


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https://reviews.llvm.org/D99324