[PATCH] D96075: [PowerPC] Exploit Prefixed Load/Stores using the refactored Load/Store Implementation

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp added a comment.

Looking at the test case changes there seem to be a few places where we are not generating expected code.
I've added comments to some of those places.



================
Comment at: llvm/test/CodeGen/PowerPC/prefixed-ld-st.ll:364
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    pstxsd v2, r3(r3), 0
+; CHECK-NEXT:    blr
----------------
Hmm... that's interesting. 
This is probably not related to this patch but this code looks odd.
For starters `pstxsd` is a D-Form instruction but we are listing two registers and no immediate. 

Also, 
```
pli r4, 4294967297
add r3, r3, r4
```
can probably be written as a `paddi`.
```
paddi r3, r3, 4294967297, 0
```
I feel like we need a TODO for this.


================
Comment at: llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll:3135
+; CHECK-P10-NEXT:    add r3, r3, r4
+; CHECK-P10-NEXT:    plfs f1, r3(r3), 0
 ; CHECK-P10-NEXT:    blr
----------------
This doesn't look right.
I assume we are trying to incorporate the `pli` into the `lfsx` but somehow the compiler gets confused and doesn't do that. Also, `plfs` is a D-Form and should have an immediate.


================
Comment at: llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll:3261
+; CHECK-P10-NEXT:    oris r3, r3, 15258
+; CHECK-P10-NEXT:    plfs f1, r3(r3), 0
 ; CHECK-P10-NEXT:    blr
----------------
We have expanded the `pli` into two instructions at this point which we shouldn't do.
Again, I think we are trying to merge `pli` and `lfsx` into `plfs` but that's not working as expected.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96075/new/

https://reviews.llvm.org/D96075