[llvm] dc206be - [ARM] Regenerate some test checks. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 24 08:34:48 PDT 2021
Author: David Green
Date: 2021-03-24T15:34:34Z
New Revision: dc206be77b329b0a83414f8c9440cb8983071622
URL: https://github.com/llvm/llvm-project/commit/dc206be77b329b0a83414f8c9440cb8983071622
DIFF: https://github.com/llvm/llvm-project/commit/dc206be77b329b0a83414f8c9440cb8983071622.diff
LOG: [ARM] Regenerate some test checks. NFC
Added:
Modified:
llvm/test/CodeGen/Thumb/cmp-add-fold.ll
llvm/test/CodeGen/Thumb/cmp-fold.ll
llvm/test/CodeGen/Thumb/ispositive.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb/cmp-add-fold.ll b/llvm/test/CodeGen/Thumb/cmp-add-fold.ll
index aa61b0825b0c..4dc0bc70440d 100644
--- a/llvm/test/CodeGen/Thumb/cmp-add-fold.ll
+++ b/llvm/test/CodeGen/Thumb/cmp-add-fold.ll
@@ -1,33 +1,65 @@
-; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK --check-prefix=T1 %s
-; RUN: llc -mtriple=thumbv7m-eabi -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK --check-prefix=T2 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs < %s | FileCheck --check-prefix=T1 %s
+; RUN: llc -mtriple=thumbv7m-eabi -verify-machineinstrs < %s | FileCheck --check-prefix=T2 %s
-; CHECK-LABEL: addri1:
-; T1: adds r0, r0, #3
-; T1-NEXT: b{{eq|ne}}
-; T2: adds r0, #3
-; T2-NOT: cmp
define i32 @addri1(i32 %a, i32 %b) {
+; T1-LABEL: addri1:
+; T1: @ %bb.0: @ %entry
+; T1-NEXT: adds r0, r0, #3
+; T1-NEXT: beq .LBB0_2
+; T1-NEXT: @ %bb.1: @ %false
+; T1-NEXT: movs r0, #5
+; T1-NEXT: bx lr
+; T1-NEXT: .LBB0_2: @ %true
+; T1-NEXT: movs r0, #4
+; T1-NEXT: bx lr
+;
+; T2-LABEL: addri1:
+; T2: @ %bb.0: @ %entry
+; T2-NEXT: adds r0, #3
+; T2-NEXT: mov.w r0, #5
+; T2-NEXT: it eq
+; T2-NEXT: moveq r0, #4
+; T2-NEXT: bx lr
+entry:
%c = add i32 %a, 3
%d = icmp eq i32 %c, 0
br i1 %d, label %true, label %false
true:
ret i32 4
+
false:
ret i32 5
}
-; CHECK-LABEL: addri2:
-; CHECK: adds r0, #254
-; T1-NEXT: b{{eq|ne}}
-; T2-NOT: cmp
define i32 @addri2(i32 %a, i32 %b) {
+; T1-LABEL: addri2:
+; T1: @ %bb.0: @ %entry
+; T1-NEXT: adds r0, #254
+; T1-NEXT: beq .LBB1_2
+; T1-NEXT: @ %bb.1: @ %false
+; T1-NEXT: movs r0, #5
+; T1-NEXT: bx lr
+; T1-NEXT: .LBB1_2: @ %true
+; T1-NEXT: movs r0, #4
+; T1-NEXT: bx lr
+;
+; T2-LABEL: addri2:
+; T2: @ %bb.0: @ %entry
+; T2-NEXT: adds r0, #254
+; T2-NEXT: mov.w r0, #5
+; T2-NEXT: it eq
+; T2-NEXT: moveq r0, #4
+; T2-NEXT: bx lr
+entry:
%c = add i32 %a, 254
%d = icmp eq i32 %c, 0
br i1 %d, label %true, label %false
true:
ret i32 4
+
false:
ret i32 5
}
diff --git a/llvm/test/CodeGen/Thumb/cmp-fold.ll b/llvm/test/CodeGen/Thumb/cmp-fold.ll
index a278e4321d03..213dfa30631a 100644
--- a/llvm/test/CodeGen/Thumb/cmp-fold.ll
+++ b/llvm/test/CodeGen/Thumb/cmp-fold.ll
@@ -1,57 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs < %s | FileCheck %s
-; CHECK-LABEL: subs:
-; CHECK: subs
-; CHECK-NEXT: b{{eq|ne}}
define i32 @subs(i32 %a, i32 %b) {
+; CHECK-LABEL: subs:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: subs r0, r0, r1
+; CHECK-NEXT: beq .LBB0_2
+; CHECK-NEXT: @ %bb.1: @ %false
+; CHECK-NEXT: movs r0, #5
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .LBB0_2: @ %true
+; CHECK-NEXT: movs r0, #4
+; CHECK-NEXT: bx lr
+entry:
%c = sub i32 %a, %b
%d = icmp eq i32 %c, 0
br i1 %d, label %true, label %false
true:
ret i32 4
+
false:
ret i32 5
}
-; CHECK-LABEL: addsrr:
-; CHECK: adds
-; CHECK-NEXT: b{{eq|ne}}
define i32 @addsrr(i32 %a, i32 %b) {
+; CHECK-LABEL: addsrr:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: adds r0, r0, r1
+; CHECK-NEXT: beq .LBB1_2
+; CHECK-NEXT: @ %bb.1: @ %false
+; CHECK-NEXT: movs r0, #5
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .LBB1_2: @ %true
+; CHECK-NEXT: movs r0, #4
+; CHECK-NEXT: bx lr
+entry:
%c = add i32 %a, %b
%d = icmp eq i32 %c, 0
br i1 %d, label %true, label %false
true:
ret i32 4
+
false:
ret i32 5
}
-; CHECK-LABEL: lslri:
-; CHECK: lsls
-; CHECK-NEXT: b{{eq|ne}}
define i32 @lslri(i32 %a, i32 %b) {
+; CHECK-LABEL: lslri:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: lsls r0, r0, #3
+; CHECK-NEXT: beq .LBB2_2
+; CHECK-NEXT: @ %bb.1: @ %false
+; CHECK-NEXT: movs r0, #5
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .LBB2_2: @ %true
+; CHECK-NEXT: movs r0, #4
+; CHECK-NEXT: bx lr
+entry:
%c = shl i32 %a, 3
%d = icmp eq i32 %c, 0
br i1 %d, label %true, label %false
true:
ret i32 4
+
false:
ret i32 5
}
-; CHECK-LABEL: lslrr:
-; CHECK: lsls
-; CHECK-NEXT: b{{eq|ne}}
define i32 @lslrr(i32 %a, i32 %b) {
+; CHECK-LABEL: lslrr:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: lsls r0, r1
+; CHECK-NEXT: beq .LBB3_2
+; CHECK-NEXT: @ %bb.1: @ %false
+; CHECK-NEXT: movs r0, #5
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .LBB3_2: @ %true
+; CHECK-NEXT: movs r0, #4
+; CHECK-NEXT: bx lr
+entry:
%c = shl i32 %a, %b
%d = icmp eq i32 %c, 0
br i1 %d, label %true, label %false
true:
ret i32 4
+
false:
ret i32 5
}
diff --git a/llvm/test/CodeGen/Thumb/ispositive.ll b/llvm/test/CodeGen/Thumb/ispositive.ll
index a9b2c139797e..950cfac8caf1 100644
--- a/llvm/test/CodeGen/Thumb/ispositive.ll
+++ b/llvm/test/CodeGen/Thumb/ispositive.ll
@@ -1,20 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s
define i32 @test1(i32 %X) {
-entry:
; CHECK-LABEL: test1:
-; CHECK: lsrs r0, r0, #31
- icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
- zext i1 %0 to i32 ; <i32>:1 [#uses=1]
- ret i32 %1
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: lsrs r0, r0, #31
+; CHECK-NEXT: bx lr
+entry:
+ icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
+ zext i1 %0 to i32 ; <i32>:1 [#uses=1]
+ ret i32 %1
}
define i32 @test2(i32 %X) {
-entry:
; CHECK-LABEL: test2:
-; CHECK: lsls r1, r1, #31
-; CHECK-NEXT: adds
- %tmp1 = sub i32 %X, 2147483648
- ret i32 %tmp1
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: movs r1, #1
+; CHECK-NEXT: lsls r1, r1, #31
+; CHECK-NEXT: adds r0, r0, r1
+; CHECK-NEXT: bx lr
+entry:
+ %tmp1 = sub i32 %X, 2147483648
+ ret i32 %tmp1
}
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