[PATCH] D98249: [SVE] Suppress vselect warning from incorrect interface call

[Nashe Mncube via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGac2a1e959690: [SVE] Suppress vselect warning from incorrect interface call (authored by nasherm).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98249/new/

https://reviews.llvm.org/D98249

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-cmp-select.ll


Index: llvm/test/CodeGen/AArch64/sve-cmp-select.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-cmp-select.ll
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=aarch64-linux-unknown -mattr=+sve -o - < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix="WARN" --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+define <vscale x 16 x i8> @vselect_cmp_ne(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+  ; CHECK-LABEL: vselect_cmp_ne
+  ; CHECK:       // %bb.0:
+	; CHECK-NEXT:    ptrue	p0.b
+	; CHECK-NEXT:    cmpne	p0.b, p0/z, z0.b, z1.b
+	; CHECK-NEXT:    sel	z0.b, p0, z1.b, z2.b
+	; CHECK-NEXT:    ret
+  %cmp = icmp ne <vscale x 16 x i8> %a, %b
+  %d = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c
+  ret <vscale x 16 x i8> %d
+}
+
+define <vscale x 16 x i8> @vselect_cmp_sgt(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+  ; CHECK-LABEL: vselect_cmp_sgt
+  ; CHECK:       // %bb.0:
+  ; CHECK-NEXT: 	ptrue	p0.b
+  ; CHECK-NEXT: 	cmpgt	p0.b, p0/z, z0.b, z1.b
+  ; CHECK-NEXT: 	sel	z0.b, p0, z1.b, z2.b
+  ; CHECK-NEXT: 	ret
+  %cmp = icmp sgt <vscale x 16 x i8> %a, %b
+  %d = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c
+  ret <vscale x 16 x i8> %d
+}
+
+define <vscale x 16 x i8> @vselect_cmp_ugt(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+  ; CHECK-LABEL: vselect_cmp_ugt
+  ; CHECK:       // %bb.0:
+  ; CHECK-NEXT: 	ptrue	p0.b
+  ; CHECK-NEXT: 	cmphi	p0.b, p0/z, z0.b, z1.b
+  ; CHECK-NEXT: 	sel	z0.b, p0, z1.b, z2.b
+  ; CHECK-NEXT: 	ret
+  %cmp = icmp ugt <vscale x 16 x i8> %a, %b
+  %d = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c
+  ret <vscale x 16 x i8> %d
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15230,7 +15230,8 @@
     }
   }
 
-  if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
+  if (N0.getOpcode() != ISD::SETCC ||
+      CCVT.getVectorElementCount() != ElementCount::getFixed(1) ||
       CCVT.getVectorElementType() != MVT::i1)
     return SDValue();
 


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