[llvm] 6204ac4 - [X86] Bale out of X86FastISel::X86SelectCmp for vectors.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-03-23T20:16:04-07:00
New Revision: 6204ac4536a4d429b83a3a984aa9bc4f5926404f

URL: https://github.com/llvm/llvm-project/commit/6204ac4536a4d429b83a3a984aa9bc4f5926404f
DIFF: https://github.com/llvm/llvm-project/commit/6204ac4536a4d429b83a3a984aa9bc4f5926404f.diff

LOG: [X86] Bale out of X86FastISel::X86SelectCmp for vectors.

None of the code in this function was written to handle
vectors.  Most of the cases already fail for vectors for one
reason or another. The exception is an optimization that
detects identical operands. This can be triggered by vectors,
but the code always creates a 0 or 1 constants in a scalar
register which is incorrect for vectors.

Fixes PR49706.

Added: 
    llvm/test/CodeGen/X86/pr49076.ll

Modified: 
    llvm/lib/Target/X86/X86FastISel.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 3d8f77ebe503..b37cd25c7de1 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -1446,6 +1446,10 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
   if (!isTypeLegal(I->getOperand(0)->getType(), VT))
     return false;
 
+  // Below code only works for scalars.
+  if (VT.isVector())
+    return false;
+
   // Try to optimize or fold the cmp.
   CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
   unsigned ResultReg = 0;

diff  --git a/llvm/test/CodeGen/X86/pr49076.ll b/llvm/test/CodeGen/X86/pr49076.ll
new file mode 100644
index 000000000000..c430ec4ff954
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr49076.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -O0 -mattr=avx | FileCheck %s
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %BB
+; CHECK-NEXT:    movb -{{[0-9]+}}(%rsp), %al
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; CHECK-NEXT:  # %bb.1: # %BB0
+; CHECK-NEXT:    vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; CHECK-NEXT:    vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT:    vpsrad $31, %xmm0, %xmm1
+; CHECK-NEXT:    vpmovsxdq %xmm1, %xmm2
+; CHECK-NEXT:    # implicit-def: $ymm0
+; CHECK-NEXT:    vmovaps %xmm2, %xmm0
+; CHECK-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; CHECK-NEXT:    vpmovsxdq %xmm1, %xmm1
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:  # %bb.2: # %BB1
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+BB:
+  %A1 = alloca i1, align 1
+  %L1 = load i1, i1* %A1, align 1
+  %Cmp = icmp ugt <4 x i64> zeroinitializer, zeroinitializer
+  br label %BB0
+
+BB0:
+  %Se = sext <4 x i1> %Cmp to <4 x i64>
+  br label %BB1
+
+BB1:
+  %Sl = select i1 %L1, <4 x i64> %Se, <4 x i64> zeroinitializer
+  ret void
+}