[PATCH] D99040: [RISCV] Add scheduler classes for the Zba and Zbb extensions.

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

This seems like a sensible level of granularity and reuse of existing resources.



================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket.td:177
 
+let Unsupported = true in {
+def : WriteRes<WriteRotateImm, []>;
----------------
Perhaps consider placing the resources for the B instructions when they are not supported in a separate file for convenient inclusion in targets which do not support it.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket.td:255
+
+let Unsupported = true in {
+def : ReadAdvance<ReadRotateImm, 0>;
----------------
Ditto.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:165
 
+let Unsupported = true in {
+def : WriteRes<WriteRotateImm, []>;
----------------
Ditto.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:243
+
+let Unsupported = true in {
+def : ReadAdvance<ReadRotateImm, 0>;
----------------
Ditto.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedule.td:93
 
+// Zba/Zbb extensions
+def WriteRotateImm   : SchedWrite;
----------------
Perhaps consider putting the resources specific to the B instructions in a separate file.


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https://reviews.llvm.org/D99040