[llvm] 75b6a47 - [AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 23 12:49:20 PDT 2021
Author: Amara Emerson
Date: 2021-03-23T12:49:10-07:00
New Revision: 75b6a47bd08292c4887b163831536f877ae9e5a6
URL: https://github.com/llvm/llvm-project/commit/75b6a47bd08292c4887b163831536f877ae9e5a6
DIFF: https://github.com/llvm/llvm-project/commit/75b6a47bd08292c4887b163831536f877ae9e5a6.diff
LOG: [AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF.
This adds some missing legalizer tests, which uncovered a v2s64 selection
test that wasn't working since there's no legalization or instruction for that.
Added:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
llvm/test/CodeGen/AArch64/arm64-clrsb.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 83ffe09612bbb..4e4d68ec57e2d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -647,6 +647,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalForCartesianProduct(
{s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.scalarize(1);
+ getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).lower();
getActionDefinitionsBuilder(G_SHUFFLE_VECTOR)
.legalIf([=](const LegalityQuery &Query) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
new file mode 100644
index 0000000000000..428a39c524863
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
@@ -0,0 +1,210 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
+---
+name: test_v8s8
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v8s8
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(<8 x s8>) = G_CTLZ [[COPY]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[CTLZ]](<8 x s8>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = G_CTLZ %0(<8 x s8>)
+ $d0 = COPY %1(<8 x s8>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v4s16
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v4s16
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(<4 x s16>) = G_CTLZ [[COPY]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[CTLZ]](<4 x s16>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = G_CTLZ %0(<4 x s16>)
+ $d0 = COPY %1(<4 x s16>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_v2s32
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_v2s32
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(<2 x s32>) = G_CTLZ [[COPY]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[CTLZ]](<2 x s32>)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = G_CTLZ %0(<2 x s32>)
+ $d0 = COPY %1(<2 x s32>)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_s64
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_s64
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[COPY1]](s64)
+ ; CHECK: $d0 = COPY [[CTLZ]](s64)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(s64) = COPY $d0
+ %2:_(s64) = COPY %0(s64)
+ %1:_(s64) = G_CTLZ %2(s64)
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: test_s32
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $s0
+ ; CHECK-LABEL: name: test_s32
+ ; CHECK: liveins: $s0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
+ ; CHECK: $s0 = COPY [[CTLZ]](s32)
+ ; CHECK: RET_ReallyLR implicit $s0
+ %0:_(s32) = COPY $s0
+ %2:_(s32) = COPY %0(s32)
+ %1:_(s32) = G_CTLZ %2(s32)
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_v16s8
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v16s8
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(<16 x s8>) = G_CTLZ [[COPY]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[CTLZ]](<16 x s8>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = G_CTLZ %0(<16 x s8>)
+ $q0 = COPY %1(<16 x s8>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v8s16
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v8s16
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(<8 x s16>) = G_CTLZ [[COPY]](<8 x s16>)
+ ; CHECK: $q0 = COPY [[CTLZ]](<8 x s16>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:_(<8 x s16>) = COPY $q0
+ %1:_(<8 x s16>) = G_CTLZ %0(<8 x s16>)
+ $q0 = COPY %1(<8 x s16>)
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: test_v4s32
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: test_v4s32
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(<4 x s32>) = G_CTLZ [[COPY]](<4 x s32>)
+ ; CHECK: $q0 = COPY [[CTLZ]](<4 x s32>)
+ ; CHECK: RET_ReallyLR implicit $q0
+ %0:_(<4 x s32>) = COPY $q0
+ %1:_(<4 x s32>) = G_CTLZ %0(<4 x s32>)
+ $q0 = COPY %1(<4 x s32>)
+ RET_ReallyLR implicit $q0
+
+...
+
+# The ZERO_UNDEF variants just lower into the vanilla ones.
+---
+name: test_s32_zeroundef
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $s0
+ ; CHECK-LABEL: name: test_s32_zeroundef
+ ; CHECK: liveins: $s0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
+ ; CHECK: $s0 = COPY [[CTLZ]](s32)
+ ; CHECK: RET_ReallyLR implicit $s0
+ %0:_(s32) = COPY $s0
+ %2:_(s32) = COPY %0(s32)
+ %1:_(s32) = G_CTLZ_ZERO_UNDEF %2(s32)
+ $s0 = COPY %1(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: test_s64_zeroundef
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: test_s64_zeroundef
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+ ; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[COPY1]](s64)
+ ; CHECK: $d0 = COPY [[CTLZ]](s64)
+ ; CHECK: RET_ReallyLR implicit $d0
+ %0:_(s64) = COPY $d0
+ %2:_(s64) = COPY %0(s64)
+ %1:_(s64) = G_CTLZ_ZERO_UNDEF %2(s64)
+ $d0 = COPY %1(s64)
+ RET_ReallyLR implicit $d0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 69d8cdec866bf..afb80021e86b6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -541,8 +541,8 @@
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_CTLZ_ZERO_UNDEF (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_CTPOP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
index 9873d49b2a388..7b0112f9e7f2b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
name: test_v8s8
alignment: 4
@@ -179,22 +179,3 @@ body: |
RET_ReallyLR implicit $q0
...
----
-name: test_v2s64
-alignment: 4
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $q0
- ; CHECK-LABEL: name: test_v2s64
- ; CHECK: liveins: $q0
- ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
- ; CHECK: [[CTLZ:%[0-9]+]]:fpr(<2 x s64>) = G_CTLZ [[COPY]](<2 x s64>)
- ; CHECK: $q0 = COPY [[CTLZ]](<2 x s64>)
- ; CHECK: RET_ReallyLR implicit $q0
- %0:fpr(<2 x s64>) = COPY $q0
- %1:fpr(<2 x s64>) = G_CTLZ %0(<2 x s64>)
- $q0 = COPY %1(<2 x s64>)
- RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/arm64-clrsb.ll b/llvm/test/CodeGen/AArch64/arm64-clrsb.ll
index 149a466a11470..412c2b00a5ac0 100644
--- a/llvm/test/CodeGen/AArch64/arm64-clrsb.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-clrsb.ll
@@ -41,3 +41,38 @@ entry:
; GISEL-LABEL: clrsb64
; GISEL: cls [[TEMP:x[0-9]+]], [[TEMP]]
}
+
+; Function Attrs: nounwind ssp
+; FALLBACK-NOT: remark{{.*}}clrsb32_zeroundef
+define i32 @clrsb32_zeroundef(i32 %x) #2 {
+entry:
+ %shr = ashr i32 %x, 31
+ %xor = xor i32 %shr, %x
+ %mul = shl i32 %xor, 1
+ %add = or i32 %mul, 1
+ %0 = tail call i32 @llvm.ctlz.i32(i32 %add, i1 true)
+
+ ret i32 %0
+; CHECK-LABEL: clrsb32_zeroundef
+; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]]
+
+; GISEL-LABEL: clrsb32_zeroundef
+; GISEL: cls [[TEMP:w[0-9]+]], [[TEMP]]
+}
+
+; Function Attrs: nounwind ssp
+; FALLBACK-NOT: remark{{.*}}clrsb64
+define i64 @clrsb64_zeroundef(i64 %x) #3 {
+entry:
+ %shr = ashr i64 %x, 63
+ %xor = xor i64 %shr, %x
+ %mul = shl nsw i64 %xor, 1
+ %add = or i64 %mul, 1
+ %0 = tail call i64 @llvm.ctlz.i64(i64 %add, i1 true)
+
+ ret i64 %0
+; CHECK-LABEL: clrsb64_zeroundef
+; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]]
+; GISEL-LABEL: clrsb64_zeroundef
+; GISEL: cls [[TEMP:x[0-9]+]], [[TEMP]]
+}
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