[PATCH] D98936: [RISCV] DAG nodes and pseudo instructions for CSR access

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff added a comment.

In D98936#2642039 <https://reviews.llvm.org/D98936#2642039>, @jrtc27 wrote:

> Are there ever any cases where you _wouldn't_ want a CSR-specific pseudo in order to have control over the scheduling of it specifically? This feels a bit like a middle-ground that's the worst of both worlds to me.

There may be cases when using registers to express dependencies is not practical. For hypothetical example, if write to some system register results in cache invalidation or in memory translation change, it is easier to model such dependency as a side effect.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:155
 
+def uimm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<12>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<12>;
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craig.topper wrote:
> Does this need to inherit from Operand? Or need any of the Parser/Encoder/MCOperand etc? Could it just be an ImmLeaf down with simm32?
Right now it may be ImmLeaf only. Changed the implementation properly.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1178
+
+let hasSideEffects = 0, isCodeGenOnly = 1 in
+def Read_CSR : Pseudo<(outs GPR:$rd), (ins csr_sysreg:$reg),
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craig.topper wrote:
> Doesn't read need side effects to say after earlier writes to it?
Indeed. Set `hasSideEffects` to true.


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