[llvm] 61fa35c - [TableGen] Allow BitsInit to init integer in pseudo expansion

[Serge Pavlov via llvm-commits]

Author: Serge Pavlov
Date: 2021-03-23T11:50:55+07:00
New Revision: 61fa35c3f7e8d06130fbee13d5620e8c3258ec5c

URL: https://github.com/llvm/llvm-project/commit/61fa35c3f7e8d06130fbee13d5620e8c3258ec5c
DIFF: https://github.com/llvm/llvm-project/commit/61fa35c3f7e8d06130fbee13d5620e8c3258ec5c.diff

LOG: [TableGen] Allow BitsInit to init integer in pseudo expansion

Differential Revision: https://reviews.llvm.org/D99057

Added: 
    llvm/test/TableGen/pseudo-inst-expansion.td

Modified: 
    llvm/utils/TableGen/PseudoLoweringEmitter.cpp

Removed: 
    


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diff  --git a/llvm/test/TableGen/pseudo-inst-expansion.td b/llvm/test/TableGen/pseudo-inst-expansion.td
new file mode 100644
index 000000000000..538d754eaf62
--- /dev/null
+++ b/llvm/test/TableGen/pseudo-inst-expansion.td
@@ -0,0 +1,37 @@
+// RUN: llvm-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def TestTargetInstrInfo : InstrInfo;
+
+def TestTarget : Target {
+  let InstructionSet = TestTargetInstrInfo;
+}
+
+def REG : Register<"REG">;
+def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
+
+class SysReg<bits<12> op> {
+  bits<12> Encoding = op;
+}
+def SR : SysReg<0b111100001111>;
+
+class Pseudo<dag outs, dag ins, list<dag> pattern>
+    : Instruction {
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let Pattern = pattern;
+  let isPseudo = 1;
+}
+
+def INSTR : Instruction {
+  let OutOperandList = (outs GPR:$rd);
+  let InOperandList = (ins i32imm:$val);
+  let Pattern = [];
+}
+
+def PSEUDO : Pseudo<(outs GPR:$rd), (ins),
+                    [(set GPR:$rd, (i32 SR.Encoding))]>,
+             PseudoInstExpansion<(INSTR GPR:$rd, SR.Encoding)>;
+
+// CHECK: .addOperand(MCOperand::createImm(3855));

diff  --git a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
index e05409db67d0..2e53e247eb99 100644
--- a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
+++ b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -108,6 +108,12 @@ addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
       OperandMap[BaseIdx + i].Kind = OpData::Imm;
       OperandMap[BaseIdx + i].Data.Imm = II->getValue();
       ++OpsAdded;
+    } else if (auto *BI = dyn_cast<BitsInit>(Dag->getArg(i))) {
+      auto II = dyn_cast<IntInit>(BI->convertInitializerTo(IntRecTy::get()));
+      assert(II && "Cannot convert to integer initializer");
+      OperandMap[BaseIdx + i].Kind = OpData::Imm;
+      OperandMap[BaseIdx + i].Data.Imm = II->getValue();
+      ++OpsAdded;
     } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
       // Just add the operands recursively. This is almost certainly
       // a constant value for a complex operand (> 1 MI operand).