[PATCH] D99128: [AMDGPU] Removed unnecessary cache invalidations.

[Steven Perron via Phabricator via llvm-commits]

s-perron created this revision.
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The SPIR-V memory barriers are translated in a very pessimistic way by
LLPC.  When translating, LLPC does know where memory will be stored, so
it will introduce a `fence` instruction.  The `fence` will eventually be
turned into an instruction to invalidate the memory cache.

If the barrier was for workgroup shared memory and all workgroup shared
variabled are allocated to LDS, then the L1 <https://reviews.llvm.org/L1> cache does not have to be
invalidated.  However, the code will still invalidate it.

This commit modifies the SI-Insert-waitcnts pass to remove cache
invalidation instructions it can prove will not be needed.  If no store
to memory that is cached reaches the cache invalidation instruction
without passing through another cache invalidation instruction, then it is
safe to remove.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99128

Files:
  llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
  llvm/test/CodeGen/AMDGPU/cache_invalidate.mir
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll

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