[PATCH] D98002: [RISCV] Add scheduling resources for V

[Evandro Menezes via Phabricator via llvm-commits]

evandro marked 11 inline comments as done.
evandro added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1349
+                       (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
+               Sched<[WriteVFMovFV, ReadVFMovFV]>;
 
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frasercrmck wrote:
> Missing read resource?
I'll have to look at the specifics of the `vd_wb` and `vd` operands.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1390
+                           (ins VR:$vs2), "vmv" # nf # "r.v", "$vd, $vs2">,
+                    Sched<[WriteVMov1V, ReadVMov1V]> {
+  let Uses = [];
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frasercrmck wrote:
> Do all nfs 1,2,4,8 have the same `1V` resource?
No, this is scrap.


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Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket.td:19
   let MispredictPenalty = 3;
+  let CompleteModel = 0;
   let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
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craig.topper wrote:
> Does anything fail without this change? I assumed the UnsupportedFeatures list covered this.
This is scrap.  Actually, I expected to need the unsupported classes list with this.  Alas, it seems to be necessary.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98002/new/

https://reviews.llvm.org/D98002