[PATCH] D98802: [RISCV][WIP] Fix offset computation for RVV

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 updated this revision to Diff 332358.
rogfer01 added a comment.

ChangeLog:

- Add comment explaining why we add the alignment of the stack as RVV padding when CSR are not aligned to 8 bytes.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98802/new/

https://reviews.llvm.org/D98802

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
  llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir

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