[PATCH] D99083: [RISCV] Introduce floating point control and state registers

Serge Pavlov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 22 08:57:38 PDT 2021


sepavloff created this revision.
sepavloff added reviewers: asb, craig.topper, luismarques, jrtc27.
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New registers FRM, FFLAGS and FCSR was defined. They represent
corresponding system registers. The new registers are necessary to
properly order floating point instructions in non-default modes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99083

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSystemOperands.td

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