[PATCH] D98628: [MCA] Disable RCU for InOrderIssueStage

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic added inline comments.


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Comment at: llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s:63
+# CHECK-NEXT: [0,1]     .DE .   add.w	r1, r1, #2
+# CHECK-NEXT: [0,2]     . DeE   vldr	d0, [r1]
 
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andreadb wrote:
> I am assuming that this change is correct.
> Not sure if we have already enough load/store tests. If not, then it may be worthy to add some tests (maybe as a follow-up. But only if you think that it is required).
No, I think the change is incorrect. Thank you very much for spotting this!  VLDR is issued 1 cycle earlier, and it does not obey to -1 `ReadAdvance` anymore.

This happens because we check `ReadAdvance` only for current `WriteState` objects. Since we now retire instructions in the same cycle as they're executed, the corresponding `WriteState` objects are also invalidated in the same cycle. A subsequent instruction cannot check for a negative `ReadAdvance` because the `WriteState` objects are invalidated at this point.

I'm thinking on how to fix this. Can we free registers when an instruction is retired, but keep `WriteState` objects for N cycles more?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98628/new/

https://reviews.llvm.org/D98628