[PATCH] D98991: [RISCV] Add support for fixed vector masked gather/scatter.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM otherwise.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3576
+// Custom lower MSCATTER to a legalized form for RVV. It will then be matched to
+// a RVV indexed load. The RVV indexed store instructions only support the
+// "unsigned unscaled" addressing mode; indices are implicitly zero-extended or
----------------
nit: `..to a RVV indexed store`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98991/new/

https://reviews.llvm.org/D98991