[PATCH] D99076: [PowerPC] [MachineLICM] Enable hoisting of caller preserved registers on AIX

[Shimin Cui via Phabricator via llvm-commits]

scui created this revision.
scui added reviewers: jsji, nemanjai, lei, Whitney, etiotto, PowerPC.
Herald added subscribers: shchenz, asbirlea, kbarton, hiraditya.
scui requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

On ppc64 linux , MachineLICM will hoist caller preserved registers, including TOC loads of the global variable address, out of loops. This is to enable this on AIX for both ppc64 and ppc32.

The performance measurements shows no negative impact on spec benchmarks.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99076

Files:
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/licm-tocReg.ll


Index: llvm/test/CodeGen/PowerPC/licm-tocReg.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/licm-tocReg.ll
+++ llvm/test/CodeGen/PowerPC/licm-tocReg.ll
@@ -1,4 +1,6 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck -check-prefixes=CHECK,CHECKLX %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECK,CHECKAIX64 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECK,CHECKAIX32 %s
 
 ; The instructions ADDIStocHA8/LDtocL are used to calculate the address of
 ; globals. The ones that are in bb.3.if.end could not be hoisted by Machine
@@ -65,22 +67,32 @@
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
-; CHECK:         addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT:    addis 5, 2, .LC1 at toc@ha
-; CHECK-NEXT:    mr 12, 3
-; CHECK-NEXT:    ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT:    ld 5, .LC1 at toc@l(5)
-; CHECK-NEXT:    lwz 6, 0(4)
-; CHECK-NEXT:    lwz 7, 0(5)
-; CHECK-NEXT:    cmpw 6, 7
-; CHECK-NEXT:    lwz 6, 0(4)
-; CHECK-NEXT:    bgt 0, .LBB0_2
-; CHECK-NOT:    addis {{[0-9]+}}, 2, .LC0 at toc@ha
-; CHECK-NOT:    addis {{[0-9]+}}, 2, .LC1 at toc@ha
-; CHECK-NEXT:    .p2align 5
-; CHECK-NEXT:  .LBB0_1: # %if.end
-; CHECK-NOT:    addis {{[0-9]+}}, 2, .LC0 at toc@ha
-; CHECK-NOT:    addis {{[0-9]+}}, 2, .LC1 at toc@ha
+; CHECKLX:        addis 4, 2, .LC0 at toc@ha
+; CHECKLX-NEXT:   addis 5, 2, .LC1 at toc@ha
+; CHECKLX-NEXT:   mr 12, 3
+; CHECKLX-NEXT:   ld 4, .LC0 at toc@l(4)
+; CHECKLX-NEXT:   ld 5, .LC1 at toc@l(5)
+; CHECKLX-NEXT:   lwz 6, 0(4)
+; CHECKLX-NEXT:   lwz 7, 0(5)
+; CHECKLX-NEXT:   cmpw 6, 7
+; CHECKLX-NEXT:   lwz 6, 0(4)
+; CHECKLX-NEXT:   bgt 0, .LBB0_2
+; CHECKLX-NOT:    addis {{[0-9]+}}, 2, .LC0 at toc@ha
+; CHECKLX-NOT:    addis {{[0-9]+}}, 2, .LC1 at toc@ha
+; CHECKLX-NEXT:   .p2align 5
+; CHECKLX-NEXT: .LBB0_1: # %if.end
+; CHECKLX-NOT:    addis {{[0-9]+}}, 2, .LC0 at toc@ha
+; CHECKLX-NOT:    addis {{[0-9]+}}, 2, .LC1 at toc@ha
+; CHECKAIX64:        ld 5, L..C0(2)
+; CHECKAIX64-NEXT:   ld 6, L..C1(2)
+; CHECKAIX64-NEXT: L..BB0_1: # %if.end
+; CHECKAIX64-NOT:    ld {{[0-9]+}}, L..C0(2)
+; CHECKAIX64-NOT:    ld {{[0-9]+}}, L..C1(2)
+; CHECKAIX32:        lwz 5, L..C0(2)
+; CHECKAIX32-NEXT:   lwz 6, L..C1(2)
+; CHECKAIX32-NEXT: L..BB0_1: # %if.end
+; CHECKAIX32-NOT:    lwz 5, L..C0(2)
+; CHECKAIX32-NOT:    lwz 6, L..C1(2)
 ; CHECK:    blr
 entry:
   %0 = load volatile i32, i32* @ga, align 4
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -403,22 +403,20 @@
   assert(Register::isPhysicalRegister(PhysReg));
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
-  if (!TM.isPPC64())
-    return false;
 
-  if (!Subtarget.isSVR4ABI())
+  if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI())
     return false;
-  if (PhysReg == PPC::X2)
-    // X2 is guaranteed to be preserved within a function if it is reserved.
+  if (PhysReg == Subtarget.getTOCPointerRegister())
+    // X2/R2 is guaranteed to be preserved within a function if it is reserved.
     // The reason it's reserved is that it's the TOC pointer (and the function
     // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
     // with no TOC access), we can't claim that it is preserved.
-    return (getReservedRegs(MF).test(PPC::X2));
-  if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects()
-      && !MFI.hasOpaqueSPAdjustment())
+    return (getReservedRegs(MF).test(PhysReg));
+  if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() &&
+      !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
     // The value of the stack pointer does not change within a function after
     // the prologue and before the epilogue if there are no dynamic allocations
-    // and no inline asm which clobbers X1.
+    // and no inline asm which clobbers X1/R1.
     return true;
   return false;
 }


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