[PATCH] D98625: [AArch64][SVE] Lower fixed length EXTRACT_VECTOR_ELT

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll:28
+; Don't use SVE for 64-bit vectors.
+define half @extractelement_v4f16(<4 x half>* %a) #0 {
+; CHECK-LABEL: extractelement_v4f16:
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The tests that take 64/128 bit vectors should pass the vector parameter directly rather than by reference.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll:55
+    %op1 = load <16 x half>, <16 x half>* %a
+    %r = extractelement <16 x half> %op1, i64 2
+    ret half %r
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Can the tests use a variable index instead? I ask because for all these tests `2` fits within the NEON range and thus when some future work lands none of these tests will emit SVE instructions.

FYI: This is also generally true as in future I'd even the variable index variants to just emit a scalar load, but this will change once all the tests are updated to use pass by value.  This is not something you need to worry about though so updating them to use a variable index is sufficient.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98625/new/

https://reviews.llvm.org/D98625