[llvm] a0f5aad - AMDGPU: Fix allowing immediates for tail call pseudo.

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-03-21T13:14:04-04:00
New Revision: a0f5aad6d7099e8ecb85f34f7a682b5d1fd088c2

URL: https://github.com/llvm/llvm-project/commit/a0f5aad6d7099e8ecb85f34f7a682b5d1fd088c2
DIFF: https://github.com/llvm/llvm-project/commit/a0f5aad6d7099e8ecb85f34f7a682b5d1fd088c2.diff

LOG: AMDGPU: Fix allowing immediates for tail call pseudo.

The pseudo was using SSrc_b64, so it allowed folding immediates into
the destination operand for a tail call to null. However, this is not
a valid operand for the s_setpc_b64 this will be lowered to. Avoids
printing the operand as an invalid immediate.

Avoids a regression when tail calls are enabled in GlobalISel (somehow
tail calls to null get deleted in the DAG).

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstructions.td
    llvm/test/MC/AMDGPU/sop1-err.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 796d85fb8af6..381f262abfea 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -479,7 +479,7 @@ def SI_CALL : SPseudoInstSI <
 
 // Tail call handling pseudo
 def SI_TCRETURN : SPseudoInstSI <(outs),
-  (ins SSrc_b64:$src0, unknown:$callee, i32imm:$fp
diff ),
+  (ins SReg_64:$src0, unknown:$callee, i32imm:$fp
diff ),
   [(AMDGPUtc_return i64:$src0, tglobaladdr:$callee, i32:$fp
diff )]> {
   let Size = 4;
   let isCall = 1;

diff  --git a/llvm/test/MC/AMDGPU/sop1-err.s b/llvm/test/MC/AMDGPU/sop1-err.s
index be88b1077f83..1593488adbcb 100644
--- a/llvm/test/MC/AMDGPU/sop1-err.s
+++ b/llvm/test/MC/AMDGPU/sop1-err.s
@@ -39,3 +39,6 @@ s_mov_b32 s103, 1
 
 s_mov_b64 s[102:103], -1
 // VI: error: register not available on this GPU
+
+s_setpc_b64 0
+// GCN: error: invalid operand for instruction