[llvm] 64c2641 - [DAG] Limit (sext_in_reg (zero_extend_vector_inreg x)) to exact sign extension

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-03-21T14:01:37Z
New Revision: 64c2641c895ab8d1d71c338294af8252969b7803

URL: https://github.com/llvm/llvm-project/commit/64c2641c895ab8d1d71c338294af8252969b7803
DIFF: https://github.com/llvm/llvm-project/commit/64c2641c895ab8d1d71c338294af8252969b7803.diff

LOG: [DAG] Limit (sext_in_reg (zero_extend_vector_inreg x)) to exact sign extension

As commented by @craig.topper on rG1ba5c550d418, we can't guarantee that we'll be extending zero bits, just sign bit. So, revert to the old code for zero_extend_vector_inreg cases.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 16833c5977d7..2f3826e45419 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11796,10 +11796,11 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
     unsigned N00Bits = N00.getScalarValueSizeInBits();
     unsigned DstElts = N0.getValueType().getVectorMinNumElements();
     unsigned SrcElts = N00.getValueType().getVectorMinNumElements();
+    bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
     APInt DemandedSrcElts = APInt::getLowBitsSet(SrcElts, DstElts);
     if ((N00Bits == ExtVTBits ||
-         (N00Bits - DAG.ComputeNumSignBits(N00, DemandedSrcElts)) <
-             ExtVTBits) &&
+         (!IsZext && (N00Bits - DAG.ComputeNumSignBits(N00, DemandedSrcElts)) <
+                         ExtVTBits)) &&
         (!LegalOperations ||
          TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT)))
       return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, N00);