[PATCH] D99029: [RISCV] Don't form MULW for (sext_inreg (mul X, Y), i32)) if the mul has another use.

[Craig Topper via Phabricator via llvm-commits]

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If this pattern doesn't fully remove the mul we'll end up with
a MUL and MULW with the same inputs.

On the assumption that multipliers are a limited resource and have
higher latency than an add, it is likely better to use a single MUL
and a sext.w instruction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99029

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoM.td
  llvm/test/CodeGen/RISCV/xaluo.ll

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