[PATCH] D98939: [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:1386
+      Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
+                         DAG.getConstant(TrueValue, dl, VT),
+                         DAG.getConstant(0, dl, VT), Tmp3);
----------------
Can we call DAG.getBoolConstant here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D98939/new/

https://reviews.llvm.org/D98939