[PATCH] D98975: [NFC][ValueTypes][RISCV]Align code by column
Shao-Ce Sun via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 19 11:53:04 PDT 2021
achieveartificialintelligence updated this revision to Diff 331966.
achieveartificialintelligence added a comment.
Resume some whitespaces.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D98975/new/
https://reviews.llvm.org/D98975
Files:
llvm/include/llvm/Support/MachineValueType.h
Index: llvm/include/llvm/Support/MachineValueType.h
===================================================================
--- llvm/include/llvm/Support/MachineValueType.h
+++ llvm/include/llvm/Support/MachineValueType.h
@@ -70,25 +70,25 @@
v512i1 = 24, // 512 x i1
v1024i1 = 25, // 1024 x i1
- v1i8 = 26, // 1 x i8
- v2i8 = 27, // 2 x i8
- v4i8 = 28, // 4 x i8
- v8i8 = 29, // 8 x i8
- v16i8 = 30, // 16 x i8
- v32i8 = 31, // 32 x i8
- v64i8 = 32, // 64 x i8
- v128i8 = 33, //128 x i8
- v256i8 = 34, //256 x i8
-
- v1i16 = 35, // 1 x i16
- v2i16 = 36, // 2 x i16
- v3i16 = 37, // 3 x i16
- v4i16 = 38, // 4 x i16
- v8i16 = 39, // 8 x i16
- v16i16 = 40, // 16 x i16
- v32i16 = 41, // 32 x i16
- v64i16 = 42, // 64 x i16
- v128i16 = 43, //128 x i16
+ v1i8 = 26, // 1 x i8
+ v2i8 = 27, // 2 x i8
+ v4i8 = 28, // 4 x i8
+ v8i8 = 29, // 8 x i8
+ v16i8 = 30, // 16 x i8
+ v32i8 = 31, // 32 x i8
+ v64i8 = 32, // 64 x i8
+ v128i8 = 33, // 128 x i8
+ v256i8 = 34, // 256 x i8
+
+ v1i16 = 35, // 1 x i16
+ v2i16 = 36, // 2 x i16
+ v3i16 = 37, // 3 x i16
+ v4i16 = 38, // 4 x i16
+ v8i16 = 39, // 8 x i16
+ v16i16 = 40, // 16 x i16
+ v32i16 = 41, // 32 x i16
+ v64i16 = 42, // 64 x i16
+ v128i16 = 43, // 128 x i16
v1i32 = 44, // 1 x i32
v2i32 = 45, // 2 x i32
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