[llvm] 95998b8 - [Hexagon] Return an i64 for result 0 from LowerREADCYCLECOUNTER instead of an i32.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-03-19T10:54:33-07:00
New Revision: 95998b898c68206bf0693cc5c1fd17ab9a395cef

URL: https://github.com/llvm/llvm-project/commit/95998b898c68206bf0693cc5c1fd17ab9a395cef
DIFF: https://github.com/llvm/llvm-project/commit/95998b898c68206bf0693cc5c1fd17ab9a395cef.diff

LOG: [Hexagon] Return an i64 for result 0 from LowerREADCYCLECOUNTER instead of an i32.

As far as I can tell, the node coming in has an i64 result so the
return should have the same type. The HexagonISD node used for
this has a type profile that says the result is i64.

Found while trying to add assserts to LegalizeDAG to catch
result type mismatches.

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D98962

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index a7e9ed34bfcb..153c7e9d9489 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -703,7 +703,7 @@ SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
   SDLoc dl(Op);
-  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
+  SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
   return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
 }