[PATCH] D98962: [Hexagon] Return an i64 for result 0 from LowerREADCYCLECOUNTER instead of an i32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added a reviewer: kparzysz.
Herald added a subscriber: hiraditya.
craig.topper requested review of this revision.
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As far as I can tell, the node coming in has an i64 result so the
return should have the same type. The HexagonISD node used for
this has a type profile that says the result is i64.

Found while trying to add assserts to LegalizeDAG to catch
result type mismatches.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98962

Files:
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp


Index: llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -703,7 +703,7 @@
                                                      SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
   SDLoc dl(Op);
-  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
+  SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
   return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
 }
 


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