[PATCH] D98956: [AArch64] Add some float -> int -> float conversion patterns

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Sounds good to me. Can we add unsigned variants too, to keep them symmetric?



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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:4752
+// avoid more costly int <-> fp register transfers.
+def : Pat<(f64 (sint_to_fp (i64 (fp_to_sint f64:$Rn)))),
+          (SCVTFv1i64 (i64 (FCVTZSv1i64 f64:$Rn)))>;
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Should we have a HasNeon predicate?


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:4756
+          (SCVTFv1i32 (i32 (FCVTZSv1i32 f32:$Rn)))>;
+def : Pat<(f16 (sint_to_fp (i32 (fp_to_sint f16:$Rn)))),
+          (SCVTFv1i16 (f16 (FCVTZSv1f16 f16:$Rn)))>;
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And for this one do we need HasFullFP16?


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  https://reviews.llvm.org/D98956/new/

https://reviews.llvm.org/D98956