[PATCH] D98920: [RISCV] Add constraint for rvv indexed loads.

Zakk Chen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 18 21:19:09 PDT 2021


khchen created this revision.
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Add the constraint when destination EEW not equals the source EEW.

The RVV spec allow three overlap rules:

1. The destination EEW equals the source EEW.

2. The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).

3. The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).

Currently I implement the first stricter constraint because I have no idea to
model other overlap rules.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98920

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

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