[llvm] c9861f7 - [RISCV] Correct the output chain in lowerFixedLengthVectorMaskedLoadToRVV

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-03-18T16:34:35-07:00
New Revision: c9861f722e375c419a07bcb70c54fe1384cd2999

URL: https://github.com/llvm/llvm-project/commit/c9861f722e375c419a07bcb70c54fe1384cd2999
DIFF: https://github.com/llvm/llvm-project/commit/c9861f722e375c419a07bcb70c54fe1384cd2999.diff

LOG: [RISCV] Correct the output chain in lowerFixedLengthVectorMaskedLoadToRVV

We returned the input chain instead of the output chain from the
new load. This bypasses the load in the chain. I haven't found a
good way to test this yet. IR order prevents my initial attempts
at causing reordering.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index bea946daa473..8c085425eb0a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3217,7 +3217,7 @@ SDValue RISCVTargetLowering::lowerFixedLengthVectorMaskedLoadToRVV(
                               Load->getMemoryVT(), Load->getMemOperand());
 
   SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget);
-  return DAG.getMergeValues({Result, Load->getChain()}, DL);
+  return DAG.getMergeValues({Result, NewLoad.getValue(1)}, DL);
 }
 
 SDValue RISCVTargetLowering::lowerFixedLengthVectorMaskedStoreToRVV(