[PATCH] D98631: AMDGPU: Fix allowing immediates for tail call pseudo.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm updated this revision to Diff 331568.
arsenm retitled this revision from "AMDGPU: Don't require registers for s_setpc_b64 operand" to "AMDGPU: Fix allowing immediates for tail call pseudo.".
arsenm edited the summary of this revision.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98631/new/

https://reviews.llvm.org/D98631

Files:
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/test/MC/AMDGPU/sop1-err.s


Index: llvm/test/MC/AMDGPU/sop1-err.s
===================================================================
--- llvm/test/MC/AMDGPU/sop1-err.s
+++ llvm/test/MC/AMDGPU/sop1-err.s
@@ -39,3 +39,6 @@
 
 s_mov_b64 s[102:103], -1
 // VI: error: register not available on this GPU
+
+s_setpc_b64 0
+// GCN: error: invalid operand for instruction
Index: llvm/lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstructions.td
+++ llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -479,7 +479,7 @@
 
 // Tail call handling pseudo
 def SI_TCRETURN : SPseudoInstSI <(outs),
-  (ins SSrc_b64:$src0, unknown:$callee, i32imm:$fpdiff),
+  (ins SReg_64:$src0, unknown:$callee, i32imm:$fpdiff),
   [(AMDGPUtc_return i64:$src0, tglobaladdr:$callee, i32:$fpdiff)]> {
   let Size = 4;
   let isCall = 1;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D98631.331568.patch
Type: text/x-patch
Size: 858 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210318/831d0fe7/attachment.bin>