[PATCH] D98779: [RISCV] Support bitcasts of fixed-length mask vectors
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 18 01:59:24 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc2b4600ec881: [RISCV] Support bitcasts of fixed-length mask vectors (authored by frasercrmck).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D98779/new/
https://reviews.llvm.org/D98779
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s
+
+define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
+; CHECK-LABEL: bitcast_v4i8_v32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT: vmxor.mm v0, v0, v8
+; CHECK-NEXT: ret
+ %c = bitcast <4 x i8> %a to <32 x i1>
+ %d = xor <32 x i1> %b, %c
+ ret <32 x i1> %d
+}
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -558,6 +558,8 @@
setOperationAction(ISD::TRUNCATE, VT, Custom);
+ setOperationAction(ISD::BITCAST, VT, Custom);
+
// Operations below are different for between masks and other vectors.
if (VT.getVectorElementType() == MVT::i1) {
setOperationAction(ISD::AND, VT, Custom);
@@ -605,8 +607,6 @@
setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
- setOperationAction(ISD::BITCAST, VT, Custom);
-
// Custom-lower reduction operations to set up the corresponding custom
// nodes' operands.
setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D98779.331488.patch
Type: text/x-patch
Size: 1812 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210318/473bcf84/attachment.bin>
More information about the llvm-commits
mailing list