[llvm] c2b4600 - [RISCV] Support bitcasts of fixed-length mask vectors

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2021-03-18T08:52:42Z
New Revision: c2b4600ec8812decfd91fd66c3db862b0fbaa6ff

URL: https://github.com/llvm/llvm-project/commit/c2b4600ec8812decfd91fd66c3db862b0fbaa6ff
DIFF: https://github.com/llvm/llvm-project/commit/c2b4600ec8812decfd91fd66c3db862b0fbaa6ff.diff

LOG: [RISCV] Support bitcasts of fixed-length mask vectors

Without this patch, bitcasts of fixed-length mask vectors would go
through the stack.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98779

Added: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4856f2c5219e..b54e2ce73fd1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -558,6 +558,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
         setOperationAction(ISD::TRUNCATE, VT, Custom);
 
+        setOperationAction(ISD::BITCAST, VT, Custom);
+
         // Operations below are 
diff erent for between masks and other vectors.
         if (VT.getVectorElementType() == MVT::i1) {
           setOperationAction(ISD::AND, VT, Custom);
@@ -605,8 +607,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
         setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
 
-        setOperationAction(ISD::BITCAST, VT, Custom);
-
         // Custom-lower reduction operations to set up the corresponding custom
         // nodes' operands.
         setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
new file mode 100644
index 000000000000..53fe40a707b5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s
+
+define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
+; CHECK-LABEL: bitcast_v4i8_v32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v0, v8
+; CHECK-NEXT:    ret
+  %c = bitcast <4 x i8> %a to <32 x i1>
+  %d = xor <32 x i1> %b, %c
+  ret <32 x i1> %d
+}